1. Field of Invention
The present invention relates to a type of chip package and fabricating method. More particularly, the present invention relates to a bridge connection type of chip package and fabricating method thereof for improving electrical performance.
2. Description of Related Art
Accompanying the rapid progress in electronic technologies, more personalized and functionally powerful electronic products are developed. To facilitate use and enhance portability, most electronic products are designed to have a lighter weight and a smaller size. Whether a given electronic product can be miniaturized depends largely on the size of the chip package embedded inside. In general, electrical connections between a silicon chip and a carrier in a chip package can be roughly divided into three major types including wire bonding, tape automated bonding (TAB) or flip chip. The connection between the contact on a chip and the contact on a carrier is made in a few sequential steps using a bonding machine. First, the bonding head of a bonding machine is driven over the contact of a chip. An electric discharge is produced near the tip of the bonding head to melt the end of the wire into a spherical ball. The spherical ball is lowered onto a chip contact to form a bond. Thereafter, the bonding head is raised pulling out additional wire from a wire spool. Finally, ultrasound is applied to melt the other end of the wire while the wire is lowered onto a carrier contact.
FIG. 1 is a cross-sectional view of a chip package having a conventional wire-bonding structure. A package structure 100 having a substrate 120, a chip 160, a plurality of conductive wires 170, an encapsulation 180 and a plurality of solder balls 190 is shown in FIG. 1. The substrate 120 has a first surface 122 and a second surface 124. The substrate 120 has a number of substrate contacts 126, 128 and a die pad 132. The contact 126 and the die pad 132 are formed on the first surface 122 of the substrate 120. The substrate contact 126 surrounds the die pad 132. The substrate contact 128 is formed on the second surface 124 of the substrate 120. The chip 160 has an active surface 162 and a backside 164. The chip 160 has a number of chip contacts 166 all on the active surface 162. The backside 164 of the chip 160 is attached to the die pad 132 of the substrate 120 through an adhesive material 140. The chip 160 and the substrate 120 are electrically connected using conductive wires positioned after a wire bonding process. One end of the conductive wire 170 is bonded to the chip contact 166 while the other end of the conductive wire 170 is bonded to the substrate contact 126. The encapsulation 180 encloses the chip 160, the first surface 122 of the substrate 120 and the conductive wires 170. The solder balls 190 are attached to the substrate contacts 128. Through the solder balls 190, the package 100 is able to connect electrically with an external circuit (not shown).
In the aforementioned package 100, the chip 160 and the substrate 120 are electrically connected through conductive wires 170. Since a conductive wire has a relatively small cross-sectional area and long length, resistant mismatch often results in signal decay. At high-frequency signaling operation, in particular, parasitic induction-capacitance in the wire may result in signal reflection. Furthermore, the small sectional area in the conductive pathway at the junction between the conductive wire 170 and the substrate contact 126 or the chip contact 166 often affects the standard power or ground voltage as well as current that ought to be supplied to the package.